Antennas for devices that employ short range, low power wireless communication can be realized using semiconductor devices. These antennas have traditionally been formed on an assembly substrate and subsequently coupled to an integrated circuit chip. Antennas of this kind are termed off-chip antennas as the antennas are not fabricated directly on the integrated circuit chip. However, as the size of communication devices has been scaled down and the used frequencies have been heading up over the years, there has been an increasing demand for more compact antenna structures. Accordingly, antennas are increasingly being fabricated directly on the integrated circuit chip, i.e., integrated with the microelectronic silicon structure. This type of antenna is termed an on-chip antenna.
A noted disadvantage of the on-chip antenna (also called an integrated antenna on silicon) is poor radiation efficiency. For a common silicon substrate thickness of about 700 μm, the radiation efficiency of an on-chip antenna can be lower than 20% of that of an equivalent antenna modeled in air. This low efficiency is due to the relatively high dielectric constant of silicon and its conductive loss. Even with a thinner silicon substrate thickness, e.g., 100 μm, the radiation efficiency of an on-chip dipole antenna is only about 60% of that of an equivalent antenna modeled in air.
Another related disadvantage of on-chip antennas is a poor peak gain due to the conductive loss and high dielectric constant of the silicon substrate. For example, the peak gain of an on-chip antenna can be at least 40% lower compared to an equivalent antenna modeled in air depending upon the silicon thickness.
One effort to improve the radiation of an on-chip antenna adds additional un-doped silicon to the substrate to form a lens. The silicon lens has a coated dielectric matching layer for impedance transformation between silicon and air to convert a surface wave in the silicon substrate to a radiation wave for improving the radiation efficiency. This method requires plural additional processing steps, which adds to the cost and complexity of manufacture. This method also disadvantageously increases the size of the chip due to the addition of the lens.